Semiconductor wafer fabrication involves a series of processes used to create semiconductor devices and integrated circuits in and on a semiconductor wafer surface. Fabrication typically involves the basic operations of layering and patterning, together with other operations such as doping and heat treatments. Layering is an operation generally used to add thick layers of material to the surface of the semiconductor wafer. Patterning is an operation that is used to remove specific portions of the top layer or layers on the wafer surface. Patterning is usually accomplished through the use of photolithography (also known as photomasking) to transfer the semiconductor design to the wafer surface.
The semiconductor devices and integrated circuits are fabricated on areas of the semiconductor wafer in repeating patterns. The individual patterns, containing the desired semiconductor devices and integrated circuits, are then separated or singulated into individual semiconductor chips, each chip possessing the desired design. The number of semiconductor chips obtained from a single semiconductor wafer is a function of the size of the starting wafer, as well as the size of the individual semiconductor chip. The separation into individual semiconductor chips is usually accomplished by cutting or scribing the semiconductor wafer, in designated regions of the wafer, located between the repeating device patterns, via use of mechanical or laser apparatus. The regions, designated as areas to be used for scribing, are usually referred to as scribe lines, or kerf regions. Since the separation into individual semiconductor chips occurs only at the completion of device fabrication process, the scribe line areas can be used for test sites or end point detection sites, needed for evaluation of the health of the ongoing semiconductor wafer. However, using scribe lines for testing presents challenges to a semiconductor manufacturing facility, also known as a foundry, for product debugging and validation.
Methods for determining compliance of chips from the foundry are important for both the foundry and chip designers in accepting lots of chips produced by the foundry for a particular set of design rules. Customers of the computer chips are generally their own chip designers providing the foundry with graphical data representing the design rules for the chips to be created on a semiconducting wafer. The foundry is then responsible for creating the chips on the semiconducting wafers to meet a set of requirements provided by the chip designers. Conventional methods using scribe line measurements to determine compliance with the design criteria serve as a basis of acceptance for the manufacturing process at the wafer test level. Since in-line testing is time consuming and expensive, it is important to perform adequate testing within a minimal amount of time. Generally, testing is done by sampling a set of scribe lines to obtain an overall health of line (‘HOL’) measurement. For customized circuits, testing by sampling may not provide an accurate assessment of device parameters with in each die (portion of the wafer containing an entire integrated circuit or collection of integrated circuits that have not been packaged) of the wafer. An accurate assessment is critical for improving yield and ensuring that customer requirements and delivery expectations are met.
Difficulties exist when using scribe line measurements, as the scribe lines are not within the actual chip boundary. Scribe line measurements can be affected by surrounding devices and may provide measurements that meet the requirements of the customer specification, while the actual device may not be in compliance. Another challenge with the use of scribe lines is that the scribe lines no longer exist after the wafers are diced. If a customer determines that there is a problem at the device level, there may be uncertainty as to where the problem originated and it can take up to approximately four to six weeks to repeat an experiment. Even with a repeat of the experiment, there may still be no definite way to determine if the problem was due to a manufacturing error, was a transient problem that no longer exists, or is a problem in the design of the chip from the customer.